EG devices require a thick silicon dioxide (SiO2) layer as a gate oxide to pass the standard reliability requirements. On the other hand, SG devices, which have a smaller fin pitch, require a thinner oxide layer to prevent the oxide from pinching off, which affects polysilicon gate reactive ion etching (PC RIE) and source/drain epitaxial (epi) growth. Currently a 3 nanometer (nm) oxide layer is being used for both EG and SG devices, since a 5 nm oxide, for example, pinches off in a 27 nm SG fin. However, the 3 nm oxide is insufficient for the EG devices.
A need therefore exists for a methodology enabling formation of a thick conformal EG oxide with a thin SG oxide and the resulting device.